• Supports 1-lane 2.5 Gb/s PCI Express.
• Utilizes 100-MHz Differential PCI Express Common Reference Clock
• Fully Compliant with PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0
• Fully Compliant with PCI Express Base Specification, Revision 1.0a
• Fully Compliant with PCI Local Bus Specification, Revision 2.3
• A Second Virtual Channel for Quality-of-Service and Isochronous Applications
• Advanced PCI Isochronous Windows for Memory Space Mapping to a Specified Traffic Class

• Fully compliant with provisions of IEEE Std 1394-1995 for high-performance serial bus and the IEEE Std 1394a-2000.
• Fully Compliant with 1394 Open Host Controller Interface Specification, Revision 1.1.
• Full IEEE Std 1394a?2000 Support Includes: Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation, Arbitration Acceleration, Fly-by Concatenation, and Port Disable/Suspend/Resume.
• Two IEEE Std 1394a-2000 Fully Compliant Cable Ports at 100M Bits/s, 200M Bits/s, and 400M Bits/s.
• EEPROM Configuration Support to Load the Global Unique ID for the 1394 Fabric.

• Support for D1, D2, D3hot, and D3cold
• Active State Link Power Management Saves Power When Packet Activity on the PCI Express Link is Idle, Using Both L0s and L1 States.
• Wake Event and Beacon Support

Two External FW-6pin